library verilog;
use verilog.vl_types.all;
entity lab3_3 is
    port(
        dig_out_021     : out    vl_logic_vector(5 downto 0);
        CLK_50MHZ_021   : in     vl_logic;
        seg_out_021     : out    vl_logic_vector(6 downto 0);
        sw_clear_021    : in     vl_logic;
        sw_stop_021     : in     vl_logic
    );
end lab3_3;
